i believe both are using the same exclusive monitor blockI see Hazard3 supports some single instruction atomic read-modify-write operations, such as AMOSWAP.W and AMOADD.W. I think Cortex-M33 lacks the corresponding ARM instructions (which were added in ARM v8.1a), though it does support such atomic operations with multiple instruction sequences using LDREX, STREX and similar. I wonder then if Hazard3 will have a performance advantage for lock-free code, particularly when there is high contention.
if anything else (including dma) writes to the addr being "atomically modified", then the write fails and it will retry
Statistics: Posted by cleverca22 — Sat Aug 10, 2024 8:55 pm