Hi Rene,
Many thanks for your reply! So the implementation is based on the principles I discovered in Sergey Matyukevich's tutorial. The kernel is loaded at physical address 0x0, but since TTBR1_EL1 is set to a PGD page table address and TCR_EL1 has T1SZ configured, the upper 16 bits of the virtual address being set simply indicates to the MMU to use the PGD table configured in TTBR1_EL1 rather than TTBR0_EL1. For all other purposes those bits are ignored. This is only really relevant/useful if the PE alternates frequently between EL0 and EL1, since it reduces the amount of TLB flushing, and admittedly at the moment my project doesn't enter EL0, but I decided to adopt it anyway in case later it does.
Note, this is all working as is right now. The issue is only if I try to change IPS / T0SZ / T1SZ settings in TCR_EL1 to increase the allowable virtual address ranges to something beyond 4GB, which I'd like to do in order to have a virtual address range for the xHCI controller. The intended change to TCR_EL1 is commented out, due to it not working, but the rest should be.
Not to worry, I mostly just wanted to check if I was doing something fundamentally wrong, e.g. to extend allowable virtual addresses ranges (i.e. the IPS / T0SZ / T1SZ settings in TCR_EL1) you first need to perform some other configuration in other ARM registers or ARM/BCM peripherals etc... I'll keep digging, and report back if I solve the issue. Thanks again though for looking into it, and taking the time to connect a debugger. Perhaps that will be my next step too - I will see if I can get something running with my existing hardware (I think I have a primitive JTAG device hanging around somewhere).
Pete
Many thanks for your reply! So the implementation is based on the principles I discovered in Sergey Matyukevich's tutorial. The kernel is loaded at physical address 0x0, but since TTBR1_EL1 is set to a PGD page table address and TCR_EL1 has T1SZ configured, the upper 16 bits of the virtual address being set simply indicates to the MMU to use the PGD table configured in TTBR1_EL1 rather than TTBR0_EL1. For all other purposes those bits are ignored. This is only really relevant/useful if the PE alternates frequently between EL0 and EL1, since it reduces the amount of TLB flushing, and admittedly at the moment my project doesn't enter EL0, but I decided to adopt it anyway in case later it does.
Note, this is all working as is right now. The issue is only if I try to change IPS / T0SZ / T1SZ settings in TCR_EL1 to increase the allowable virtual address ranges to something beyond 4GB, which I'd like to do in order to have a virtual address range for the xHCI controller. The intended change to TCR_EL1 is commented out, due to it not working, but the rest should be.
Not to worry, I mostly just wanted to check if I was doing something fundamentally wrong, e.g. to extend allowable virtual addresses ranges (i.e. the IPS / T0SZ / T1SZ settings in TCR_EL1) you first need to perform some other configuration in other ARM registers or ARM/BCM peripherals etc... I'll keep digging, and report back if I solve the issue. Thanks again though for looking into it, and taking the time to connect a debugger. Perhaps that will be my next step too - I will see if I can get something running with my existing hardware (I think I have a primitive JTAG device hanging around somewhere).
Pete
Statistics: Posted by pmoore — Fri Dec 06, 2024 8:52 pm