Oh I like this question/point. I would recommend using deferred interrupt processing. This generally requires an operating system which can be somewhat taxing in terms of resources. I would also avoid full SMP, but that is more paranoid than anything in the RP2040. (Core 0 runs OS and core 1 is delegate of core 0.)
Most of the APIs are pure functional programming. The more manger APIs are not pure and should not be trusted. Most accesses are volatile and this should be taken into account. So coherency, re-entrance, deadlock, etc. tend to be mitigated somewhat by these properties. Pushing to a UART FIFO is a violation of recommended design patterns, however this is volatile and you must force atomic to ensure order. The SDK and hardware will not do this for you.
Designing software to be pure and lockless is generally best. Lockless algorithm design is much more difficult than just creating exclusion zones of single threaded. Lockless, priority, operation per second, memory management, etc. are very important in this environment. These you are ultimately responsible for.
Generally I run up behind the SDK and snoop the code before I use it. I also only consume a specific SDK release once this has been done. Periodically I will look at my output to see if it is as expected. (Annoying but worth it in some cases, like RAM functions.)
Cortex-M0+ is not big on reordering like larger notions of ARM. RP2040 is not true SMP. RP2040 keeps with certain traditions that generally work but in a less formal way. They will likely move to a more formal approach in the future.
Most of the APIs are pure functional programming. The more manger APIs are not pure and should not be trusted. Most accesses are volatile and this should be taken into account. So coherency, re-entrance, deadlock, etc. tend to be mitigated somewhat by these properties. Pushing to a UART FIFO is a violation of recommended design patterns, however this is volatile and you must force atomic to ensure order. The SDK and hardware will not do this for you.
Designing software to be pure and lockless is generally best. Lockless algorithm design is much more difficult than just creating exclusion zones of single threaded. Lockless, priority, operation per second, memory management, etc. are very important in this environment. These you are ultimately responsible for.
Generally I run up behind the SDK and snoop the code before I use it. I also only consume a specific SDK release once this has been done. Periodically I will look at my output to see if it is as expected. (Annoying but worth it in some cases, like RAM functions.)
Cortex-M0+ is not big on reordering like larger notions of ARM. RP2040 is not true SMP. RP2040 keeps with certain traditions that generally work but in a less formal way. They will likely move to a more formal approach in the future.
Statistics: Posted by dthacher — Sat Feb 24, 2024 2:25 pm